EM250
SC2_DMASTAT [0x4416]
15
0-R
0
0
0-R
7
14
0-R
0
0
0-R
6
13
0-R
0
SC_RXOVFB
0-R
5
12
0-R
0
SC_RXOVFA
0-R
4
11
0-R
0
SC_TXACTB
0-R
3
10
0-R
0
SC_TXACTA
0-R
2
9
0-R
0
SC_RXACTB
0-R
1
8
0-R
0
SC_RXACTA
0-R
0
SC_RXOVFB
SC_RXOVFA
SC_TXACTB
SC_TXACTA
SC_RXACTB
SC_RXACTA
[5]
[4]
[3]
[2]
[1]
[0]
This bit is set when DMA receive buffer B was passed an overrun error from the lower
hardware FIFO. Neither receive buffers were capable of accepting any more bytes
(unloaded), and the FIFO filled up. Buffer B was the next buffer to load, and when it
drained the FIFO the overrun error was passed up to the DMA and flagged with this bit. This
bit is autocleared the next time buffer B is loaded or when the receive DMA is reset.
This bit is set when DMA receive buffer A was passed an overrun error from the lower
hardware FIFO. Neither receive buffers were capable of accepting any more bytes
(unloaded), and the FIFO filled up. Buffer A was the next buffer to load, and when it
drained the FIFO the overrun error was passed up to the DMA and flagged with this bit. This
bit is autocleared the next time buffer A is loaded or when the receive DMA is reset.
This bit is set when DMA transmit buffer B is currently active.
This bit is set when DMA transmit buffer A is currently active.
This bit is set when DMA receive buffer B is currently active.
This bit is set when DMA receive buffer A is currently active.
SC2_RXCNTA [0x4410]
15
0-R
14
0-R
13
0-R
12
0-R
11
0-R
10
0-R
9
0-R
8
0-R
0
0
0
SC2_RXCNTA
SC2_RXCNTA
0-R
7
0-R
6
0-R
5
0-R
4
0-R
3
0-R
2
0-R
1
0-R
0
SC2_RXCNTA
[12:0]
A byte offset (from 0) which points to the location in DMA receive buffer A where the next
byte will be written. When the buffer fills and subsequently unloads, this register wraps
around and holds the value zero (pointing back to the first location in the buffer).
Page 73
120-0082-000V Rev 1.1
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